Air gaps formed by porous silicon removal

ABSTRACT

Semiconductor structures formed using a substrate that has a porous semiconductor layer and a device layer on the porous semiconductor layer. One or more trench isolation regions are formed in the device layer that surround an active device region. An opening is formed that extends through the one or more trench isolation regions to the porous semiconductor layer. A removal agent is directed through the opening to remove the porous semiconductor layer from a volume beneath the active device region and thereby form an air gap vertically beneath the active device region.

BACKGROUND

The invention relates generally to semiconductor devices and integratedcircuit fabrication and, in particular, to semiconductor structures foran active device region and methods of forming such semiconductorstructures.

Devices fabricated using semiconductor-on-insulator (SOI) technologiesmay exhibit certain performance improvements in comparison withcomparable devices built directly in a bulk silicon substrate.Generally, an SOI wafer includes a thin device layer of semiconductormaterial, a handle substrate, and a thin buried insulator layer, such asa buried oxide or BOX layer, physically separating and electricallyisolating the device layer from the handle substrate. Integratedcircuits are fabricated using the semiconductor material of the devicelayer. A primary source of the improved performance is due to thepresence of the BOX layer.

Improved semiconductor structures for an active device region andmethods of forming such semiconductor structures are needed.

SUMMARY

In an embodiment of the invention, a method is provided for forming asemiconductor structure using a substrate that has a poroussemiconductor layer and a device layer on the porous semiconductorlayer. One or more trench isolation regions are formed in the devicelayer that surround an active device region. An opening is formed thatextends through the one or more trench isolation regions to the poroussemiconductor layer. A removal agent is directed through the opening toremove the porous semiconductor layer from a volume beneath the activedevice region and thereby form an air gap vertically beneath the activedevice region such that the active device layer is supported.

In an embodiment of the invention, a device structure is formed using asubstrate that has a porous semiconductor layer and a device layer onthe porous semiconductor layer. The semiconductor structure includes oneor more trench isolation regions in the device layer and an air gap inthe porous semiconductor layer. The one or more trench isolation regionssurround an active device region. The air gap is vertically locatedbeneath the active device region and laterally located between a firstsection of the porous semiconductor layer and a second section of theporous semiconductor layer. The first section of the poroussemiconductor layer and the second section of the porous semiconductorlayer are located beneath the active device region such that the activedevice layer is supported.

BRIEF DESCRIPTION OF THE DRAWINGS

The accompanying drawings, which are incorporated in and constitute apart of this specification, illustrate various embodiments of theinvention and, together with a general description of the inventiongiven above and the detailed description of the embodiments given below,serve to explain the embodiments of the invention.

FIGS. 1-4 are cross-sectional views of a portion of a substrate atsuccessive stages of a processing method for fabricating a structure fora device region in accordance with an embodiment of the invention.

FIG. 5 is a top view of the structure of FIG. 4 in which the devicestructures and protective layer are omitted for purposes of clarity ofdescription.

DETAILED DESCRIPTION

With reference to FIG. 1 and in accordance with an embodiment of theinvention, a substrate 10 comprises a single-crystal semiconductormaterial, such as silicon, usable to form the devices of an integratedcircuit. Substrate 10 may be, for example, a bulk silicon wafer or anactive silicon SOI layer of a silicon-on-insulator wafer. At its topsurface, the substrate 10 may include a device layer 12, which maycontain an amount of an electrically-active dopant that enhances itselectrical properties relative to the remainder of the substrate 10.

The substrate 10 further includes a porous semiconductor layer 14 thatis located beneath the device layer 12 at the top surface of thesubstrate 10 and a handle wafer 11. In an embodiment of the invention,the porous semiconductor layer 14 may be formed by converting thesemiconductor material (e.g. silicon) of a seed wafer to a poroussemiconductor material (e.g., porous silicon) using an anodizationprocess performed using an aqueous electrolyte or anodization solutioncontaining hydrofluoric acid (HF), such as a solution of hydrofluoricacid and a monohydric alcohol like ethanol. The seed wafer is contactedwith a biased electrode and immersed, along with a separateoppositely-biased electrode, into a bath of the anodization solution. Anelectrical current is passed through the electrodes and the seed waferfor an anodization time sufficient to convert the heavily doped siliconto porous silicon and complete the process forming the poroussemiconductor layer 14. The anodization process creates pores across thedepth of the porous semiconductor layer 14 in which the resultingporosity may be proportional to factors such as current density. Forexample, the porous semiconductor layer 14 may include sub-layers ofdiffering porosity may be formed by changing the current density duringanodization to two different values. The surface of the poroussemiconductor layer 14 may be smoothed and the pores at its surfacesealed by, for example, a combination of a wet etch using a solutioncontaining hydrofluoric acid and hydrogen peroxide (H₂O₂) and asubsequent thermal anneal in a hydrogen-rich atmosphere. The devicelayer 12 may then be formed on the sealed and smoothed surface by, forexample, an epitaxial deposition process involving chemical vapordeposition (CVD). The device layer 12 and porous semiconductor layer 14may then be transferred to the substrate 10 by a transfer process.

Trench isolation regions 16 are located in the semiconductor material ofthe substrate 10. An active device region 18 used in fabricating adevice structure is bounded by the trench isolation regions 16. Theactive device region 18 is comprised of a portion of the semiconductormaterial of the device layer 12, and has an outer boundary 17established in part by location of the trench isolation regions 16. Thetrench isolation regions 16 extend from the top surface of the devicelayer 12 to a shallow depth beneath the top surface. The trenchisolation regions 16 may be formed by forming an etch mask usingphotolithography and etching to define trenches, followed by filling thetrenches with a dielectric material, such as silicon dioxide (SiO₂)deposited by chemical vapor phase deposition and subsequentlyplanarized.

With reference to FIG. 2 in which like reference numerals refer to likefeatures in FIG. 1 and at a subsequent fabrication stage of theprocessing method, the trench isolation regions 16 are etched andpartially removed in the presence of a mask to form an openings 19 thatextend completely through the trench isolation regions 16 to theunderlying porous semiconductor layer 14. The etchant used to remove theportions of the trench isolation regions 16 to form the openings 19 maybe a buffered hydrofluoric acid (BHF) solution, which removes silicondioxide selective to (i.e., at a higher etch rate than) silicon. Otherportions of the trench isolation regions 16 located laterally betweenthe openings 19 and the active device region 18 are protected andpreserved due to the presence of the mask.

Oxidized regions 20 are formed in the semiconductor material of theporous semiconductor layer 14. The oxidized regions 20 may be formedusing a wet or dry thermal oxidation process and with the same mask usedto form the openings 19 present. The oxidation agent used to form theoxidized regions 20 is directed through the openings 19 to the poroussemiconductor layer 14. Due to its porosity, the porous semiconductorlayer 14 may more readily oxidize than the semiconductor material of thesubstrate 10 underlying the oxidized regions 20, which may serve toconfine the depth of oxidation to the thickness of the poroussemiconductor layer 14. The oxidation may proceed laterally beneath thetrench isolation regions 16 such that portions of the oxidized regions20 are located beneath the trench isolation regions 16. The oxidizedregions 20 laterally bound a section 15 of the porous semiconductorlayer 14.

With reference to FIG. 3 in which like reference numerals refer to likefeatures in FIG. 2 and at a subsequent fabrication stage of theprocessing method, a layer 22 is deposited and patterned. The layer 22is comprised of a material that etches selective to (i.e., at a higheretch rate than) the materials of the trench isolation regions 16 and theactive device region 18. The layer 22 covers the oxidized regions 20 andoverlaps with a portion of the trench isolation regions 16 adjacent tothe oxidized regions 20. A mask present during deposition defines thelocations at which the layer 22 is present and absent. The mask may bethe same mask used during the prior etching process partially removingthe trench isolation regions 16. The layer 22 may be comprised of adielectric layer, such as silicon nitride (Si₃N₄), deposited by chemicalvapor deposition and etched by an etching process, such as reactive ionetching.

The trench isolation regions 16 are etched and partially removed overareas not covered by the layer 22. The etchant, which removes thematerial of the trench isolation regions 16 selective to the material ofthe active device region 18, may be a buffered hydrofluoric acid (BHF)solution. Portions of the trench isolation regions 16 adjacent to andbordering the active device region 18 are removed by the etch totrenches defining openings 24 extending through the trench isolationregions 16 to the section 15 of the porous semiconductor layer 14. Otherportions of the trench isolation regions 16 laterally separated from theactive device region 18 by the openings 24 are protected and preserveddue to the presence of the layer 22.

The oxidized regions 20 are protected during etching and preserved dueto the presence of the layer 22, and the semiconductor material of theactive device region 18 is unaffected by the etching process. The outerboundary 17 of the active device region 18 is located adjacent to theopenings 24 following the partial removal of the trench isolationregions 16. The openings 24 are located laterally between the residualportions of the trench isolation regions 16 and the active device region18.

With reference to FIGS. 4, 5 in which like reference numerals refer tolike features in FIG. 3 and at a subsequent fabrication stage of theprocessing method, one or more device structures 40, such as one or morefield effect transistors, are formed using the active device region 18during front-end-of-line (FEOL) processing. The device structure(s) 40and active device region 18 are covered by a protective barrier layer41, such as by a layer of silicon nitride deposited by chemical vapordeposition, to prevent modification of the device structure(s) 40 andactive device region 18 when subsequently forming the air gap 26.

The section 15 of the porous semiconductor layer 14 is removed to forman air gap 26. The section 15 of the porous semiconductor layer 14functions as a temporary, sacrificial material that occupies the spaceopened at this juncture of the processing method to define the air gap26. The air gap 26 may have nominally the same volume as the section 15of the porous semiconductor layer 14 that is removed. The oxidizedregions 20 limit the space over which the section 15 of the poroussemiconductor layer 14 is removed, and laterally bound the air gap 26after the section 15 is removed.

The section 15 of the porous semiconductor layer 14 may be removed usinga removal agent, such as etchant solution (e.g., dilute potassiumhydroxide (1% KOH in water)), that is directed through the openings 24.The removal agent interacts with the section 15 of the poroussemiconductor layer 14 and causes its removal outward through theopenings 24. In the representative embodiments, the etchant solution maybe heated and/or supplied under high pressure, such as being forcedthrough the openings 24 under a pressure of 2 to 3 atmospheres. In anembodiment, The process removing the section 15 of the poroussemiconductor layer 14 does not rely on an acid as an etchant. Theoxidized regions 20 are unaffected by the process removing the section15 of the porous semiconductor layer 14, and are intact following itsremoval.

The air gap 26 is vertically located beneath the active device region 18between the handle wafer 11 and the active device region 18. Morespecifically, the air gap 26 is vertically located beneath a beam orbridge 28 of the active device region 18, as diagrammaticallyillustrated by the dashed lines in FIG. 5. The openings 24 are laterallylocated between the side edges 29, 31 of the bridge 28 and respectivetrench isolation regions 16 such that the bridge 28 is not connected orsupported at its side edges 29, 31. The porous semiconductor layer 14 isnot removed from underneath sections 30, 32 of the active device region18. The bridge 28 extends laterally from one end integrally attached tothe section 30 of the active device region 18 to an opposite endintegrally attached to the section 32 of the active device region 18.The sections 30, 32 of the active device region 18 directly support thebridge 28.

The porous semiconductor material in the sections 34, 36 of the poroussemiconductor layer 14 is neither oxidized nor removed, and thesesections 34, 36 are respectively located beneath the sections 30, 32 ofthe active device region 18. The bridge 28 is also laterally locatedbetween these sections 34, 36 of the porous semiconductor layer 14. Theremoval process is controlled (e.g., timed) such that these sections 34,36 of the porous semiconductor layer 14 are not removed when thesacrificial section 15 is removed. These sections 34, 36 of the poroussemiconductor layer 14 directly support the sections 30, 32 of theactive device region 18 and thereby indirectly support the bridge 28.

The air gap 26 may be characterized by an effective permittivity ordielectric constant of near unity (vacuum permittivity), or may befilled by air at or near atmospheric pressure, may be filled by anothergas at or near atmospheric pressure, or may contain air or another gasat a sub-atmospheric pressure (e.g., a partial vacuum). The “silicon onnothing” architecture provides efficient electrical isolation for theone or more device structures 40.

The methods as described above are used in the fabrication of integratedcircuit chips. The resulting integrated circuit chips can be distributedby the fabricator in raw wafer form (e.g., as a single wafer that hasmultiple unpackaged chips), as a bare die, or in a packaged form. In thelatter case, the chip is mounted in a single chip package (e.g., aplastic carrier, with leads that are affixed to a motherboard or otherhigher level carrier) or in a multichip package (e.g., a ceramic carrierthat has either or both surface interconnections or buriedinterconnections). In any case, the chip may be integrated with otherchips, discrete circuit elements, and/or other signal processing devicesas part of either an intermediate product or an end product.

References herein to terms such as “vertical”, “horizontal”, etc. aremade by way of example, and not by way of limitation, to establish aframe of reference. The term “horizontal” as used herein is defined as aplane parallel to a conventional plane of a semiconductor substrate,regardless of its actual three-dimensional spatial orientation. Theterms “vertical” and “normal” refer to a direction perpendicular to thehorizontal, as just defined. The term “lateral” refers to a directionwithin the horizontal plane. Terms such as “above” and “below” are usedto indicate positioning of elements or structures relative to each otheras opposed to relative elevation.

A feature “connected” or “coupled” to or with another element may bedirectly connected or coupled to the other element or, instead, one ormore intervening elements may be present. A feature may be “directlyconnected” or “directly coupled” to another element if interveningelements are absent. A feature may be “indirectly connected” or“indirectly coupled” to another element if at least one interveningelement is present.

The descriptions of the various embodiments of the present inventionhave been presented for purposes of illustration, but are not intendedto be exhaustive or limited to the embodiments disclosed. Manymodifications and variations will be apparent to those of ordinary skillin the art without departing from the scope and spirit of the describedembodiments. The terminology used herein was chosen to best explain theprinciples of the embodiments, the practical application or technicalimprovement over technologies found in the marketplace, or to enableothers of ordinary skill in the art to understand the embodimentsdisclosed herein.

What is claimed is:
 1. A method of forming a semiconductor structureusing a substrate that has a porous semiconductor layer and a devicelayer on the porous semiconductor layer, the method comprising: formingone or more trench isolation regions in the device layer that surroundan active device region; forming an opening extending through the one ormore trench isolation regions to the porous semiconductor layer; forminga protective layer on the active device region; and directing a removalagent through the opening to remove the porous semiconductor layer froma volume beneath the active device region and thereby form an air gapvertically beneath the active device region.
 2. The method of claim 1wherein the air gap is laterally located between a first section of theporous semiconductor layer and a second section of the poroussemiconductor layer, and the first section of the porous semiconductorlayer and the second section of the porous semiconductor layer arelocated beneath the active device region and support the active deviceregion.
 3. The method of claim 1 wherein the removal agent is an etchantsolution supplied to the opening at a pressure exceeding one atmosphericpressure.
 4. The method of claim 1 further comprising: before theopening is formed, removing a second section of the one or more trenchisolation regions to expose the porous semiconductor layer; andoxidizing the porous semiconductor layer exposed by the removal of thesecond section of the one or more trench isolation regions to form anoxidized section, wherein the oxidized section is coextensive with theair gap.
 5. The method of claim 4 wherein the oxidized section is notremoved when the removal agent is directed through the opening to removethe porous semiconductor layer from the volume beneath the active deviceregion.
 6. The method of claim 1 further comprising: before the removalagent is directed through the opening, forming a device structure usingthe active device region.
 7. The method of claim 1 wherein the substratefurther includes a handle wafer, the porous semiconductor layer isvertically located between the device layer and the handle wafer, andthe air gap is vertically located between the active device region andthe handle wafer.